عبدالعليم نور الدين
25-11-07, 02:53 PM
Power Distribution Network Design for VLSI
http://www.sayedsaad.com/montada/imgcache/2131.imgcache (http://pixhost.eu/avaxhome/big_show.php?/avaxhome/2007-11-19/411_orig.jpg)
Qing K. Zhu "Power Distribution Network Design for VLSI"
Publisher: Wiley-Interscience | Pages: 207 | 2004-02-19 | ISBN:0471657204 | PDF | 4,8 Mb
A hands-on troubleshooting guide for VLSI network designers
The primary goal in VLSI (very large scale integration) power network design is to provide enough power lines across a chip to reduce voltage drops from the power pads to the center of the chip. Voltage drops caused by the power network’s ****l lines coupled with transistor switching currents on the chip cause power supply noises that can affect circuit timing and performance, thus providing a constant challenge for designers of high-performance chips.
Power Distribution Network Design for VLSI provides detailed information on this critical component of circuit design and physical integration for high-speed chips. A vital tool for professional engineers (especially those involved in the use of commercial tools), as well as graduate students of engineering, the **** explains the design issues, guidelines, and CAD tools for the power distribution of the VLSI chip and package, and provides numerous examples for its effective application.
NO Mirrors Pls
http://rapidshare. com/files/ 70357789/ Power_Distributi on_Network_ Design_For_ VLSI.rar (http://rapidshare.com/files/70357789/Power_Distribution_Network_Design_For_VL SI.rar)
http://www.sayedsaad.com/montada/imgcache/2131.imgcache (http://pixhost.eu/avaxhome/big_show.php?/avaxhome/2007-11-19/411_orig.jpg)
Qing K. Zhu "Power Distribution Network Design for VLSI"
Publisher: Wiley-Interscience | Pages: 207 | 2004-02-19 | ISBN:0471657204 | PDF | 4,8 Mb
A hands-on troubleshooting guide for VLSI network designers
The primary goal in VLSI (very large scale integration) power network design is to provide enough power lines across a chip to reduce voltage drops from the power pads to the center of the chip. Voltage drops caused by the power network’s ****l lines coupled with transistor switching currents on the chip cause power supply noises that can affect circuit timing and performance, thus providing a constant challenge for designers of high-performance chips.
Power Distribution Network Design for VLSI provides detailed information on this critical component of circuit design and physical integration for high-speed chips. A vital tool for professional engineers (especially those involved in the use of commercial tools), as well as graduate students of engineering, the **** explains the design issues, guidelines, and CAD tools for the power distribution of the VLSI chip and package, and provides numerous examples for its effective application.
NO Mirrors Pls
http://rapidshare. com/files/ 70357789/ Power_Distributi on_Network_ Design_For_ VLSI.rar (http://rapidshare.com/files/70357789/Power_Distribution_Network_Design_For_VL SI.rar)